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| CY7C1021BN CY7C10211BN 1-Mbit (64K x 16) Static RAM Features * Temperature Ranges -- Commercial: 0C to 70C -- Industrial: -40C to 85C -- Automotive-A: -40C to 85C -- Automotive-E: -40C to 125C * High speed -- tAA = 10 ns (Commercial) -- tAA = 15 ns (Automotive) * CMOS for optimum speed/power * Low active power -- 825 mW (max.) * Automatic power-down when deselected * Independent control of upper and lower bits * Available in Pb free and non Pb free 44-pin TSOP II and 44-pin 400-mil-wide SOJ Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021BN/CY7C10211BN is available in standard 44-pin TSOP Type II and 44-pin 400-mil-wide SOJ packages. Customers should use part number CY7C10211BN when ordering parts with 10 ns tAA, and CY7C1021BN when ordering 12 ns and 15 ns tAA. Functional Description[1] The CY7C1021BN/CY7C10211BN is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Logic Block Diagram Pin Configurations DATA IN DRIVERS A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC SOJ / TSOP II Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A7 A6 A5 A4 A3 A2 A1 A0 64K x 16 RAM Array 512 X 2048 I/O1-I/O8 I/O9-I/O16 COLUMN DECODER BHE WE CE OE BLE A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC ROW DECODER Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com Cypress Semiconductor Corporation Document #: 001-06494 Rev. *A A8 A9 A10 A11 A12 A13 A14 A15 SENSE AMPS * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised September 28, 2006 [+] Feedback CY7C1021BN CY7C10211BN Selection Guide 7C10211B-10 Maximum Access Time (ns) Maximum Operating Current (mA) Com'l / Ind'l Automotive-A Automotive-E Maximum CMOS Standby Current (mA) Com'l / Ind'l Com'l / Ind'l (L version) Automotive-A (L version) Automotive-E 10 0.5 10 0.5 10 150 7C1021B-12 12 140 7C1021B-15 15 130 130 130 10 0.5 0.5 15 Pin Definitions Pin Name A0-A15 I/O1-I/O16 NC WE CE BHE, BLE OE SOJ, TSOP-Pin Number 1-5,18-21, 24-27, 42-44 7-10, 13-16, 29-32, 35-38 22, 23, 28 17 6 40, 39 41 I/O Type Input Description Address Inputs used to select one of the address locations. Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation. No Connect No Connects. Not connected to the die. Input/Control Write Enable Input, active LOW. When selected LOW, a Write is conducted. When deselected HIGH, a Read is conducted. Input/Control Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input/Control Byte Write Select Inputs, active LOW. BHE controls I/O16-I/O9, BLE controls I/O8-I/O1, . Input/Control Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. Ground Ground for the device. Should be connected to ground of the system. VSS VCC 12, 34 11, 33 Power Supply Power Supply inputs to the device. Document #: 001-06494 Rev. *A Page 2 of 10 [+] Feedback CY7C1021BN CY7C10211BN Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC Relative to GND[2] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ......................................-0.5V to VCC+0.5V DC Input Voltage[2] ...................................-0.5V to VCC+0.5V Current into Outputs (LOW) .........................................20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial Industrial Automotive-A Automotive-E Ambient Temperature (TA)[3] 0C to +70C -40C to +85C -40C to +85C -40C to +125C VCC 5V 10% Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current GND < VI < VCC Com'l / Ind'l Automotive-A Automotive-E IOZ Output Leakage GND < VI < VCC, Current Output Disabled Com'l / Ind'l Automotive-A Automotive-E ICC VCC Operating VCC = Max., Supply Current IOUT = 0 mA, f = fMAX = 1/tRC Automatic CE Power-Down Current--TTL Inputs Automatic CE Power-Down Current-- CMOS Inputs Com'l / Ind'l Automotive-A Automotive-E 40 40 150 140 -1 +1 -1 +1 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -1 -10 Min. 2.4 0.4 6.0 0.8 +1 2.2 -0.5 -1 Max. Min. 2.4 0.4 6.0 0.8 +1 2.2 -0.5 -1 -1 -4 -1 -1 -4 -12 Max. Min. 2.4 0.4 6.0 0.8 +1 +1 +4 +1 +1 +4 130 130 130 40 40 50 10 0.5 10 0.5 10 0.5 0.5 15 mA mA -15 Max. Unit V V V V A A A A A A mA ISB1 Max. VCC, Com'l / Ind'l CE > VIH Automotive-A VIN > VIH or VIN < VIL, f = fMAX Automotive-E Max. VCC, Com'l / Ind'l CE > VCC - 0.3V, Com'l / Ind'l (L) VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Automotive-A (L) Automotive-E ISB2 Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF Notes: 2. VIL (min.) = -2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 3. TA is the "Instant On" case temperature. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06494 Rev. *A Page 3 of 10 [+] Feedback CY7C1021BN CY7C10211BN Thermal Resistance[4] Parameter Description Test Conditions 44-pin SOJ 64.32 31.03 44-pin TSOP-II 76.89 14.28 Unit C/W C/W JA JC Thermal Resistance Test conditions follow standard test methods (Junction to Ambient) and procedures for measuring thermal Thermal Resistance impedance, per EIA / JESD51. (Junction to Case) AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 255 255 R 481 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) 167 30 pF R2 255 255 GND R 481 3.0V 90% 10% ALL INPUT PULSES 90% 10% Rise Time: 1 V/ns Fall Time: 1 V/ns OUTPUT Equivalent to: THEVENIN EQUIVALENT 1.73V Switching Characteristics[5] Over the Operating Range 7C10211B-10 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[6] Z[6, 7] 3 5 0 10 5 0 5 0 6 0 12 6 0 7 Z[6, 7] 0 5 3 6 0 15 7 OE HIGH to High CE HIGH to High 3 10 5 0 6 3 7 10 10 3 12 6 0 7 12 12 3 15 7 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C1021B-12 Min. Max. 7C1021B-15 Min. Max. Unit CE LOW to Low Z[6] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. Document #: 001-06494 Rev. *A Page 4 of 10 [+] Feedback CY7C1021BN CY7C10211BN Switching Characteristics[5] Over the Operating Range (continued) 7C10211B-10 Parameter Write Cycle tWC tSCE tAW tHA tSA tSD tHD tLZWE tHZWE tBW [8] 7C1021B-12 Min. 12 9 8 0 0 6 0 3 Max. 7C1021B-15 Min. 15 10 10 0 0 8 0 3 Max. Unit ns ns ns ns ns ns ns ns 7 9 ns ns Description Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z [6] [6, 7] Min. 10 8 7 0 0 5 0 3 Max. 5 7 8 6 Byte Enable to End of Write Switching Waveforms Read Cycle No. 1[9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE DATA OUT HIGH IMPEDANCE Notes: 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 10. WE is HIGH for read cycle. Document #: 001-06494 Rev. *A Page 5 of 10 [+] Feedback CY7C1021BN CY7C10211BN Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[12, 13] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW BHE, BLE tSD DATA I/O tHD tHA Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATA I/O tHD tHA Notes: 11. Address valid prior to or coincident with CE transition LOW. 12. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 001-06494 Rev. *A Page 6 of 10 [+] Feedback CY7C1021BN CY7C10211BN Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS CE tSCE tAW tSA tPWE tHA WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD Truth Table CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1-I/O8 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z I/O9-I/O16 High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Power-Down Read - All bits Read - Lower bits only Read - Upper bits only Write - All bits Write - Lower bits only Write - Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 001-06494 Rev. *A Page 7 of 10 [+] Feedback CY7C1021BN CY7C10211BN Ordering Information Speed (ns) 10 12 Ordering Code CY7C10211BN-10ZXC CY7C1021BN-12VC CY7C1021BN-12VXC CY7C1021BN-12ZC CY7C1021BN-12ZXC CY7C1021BN-12VI CY7C1021BN-12VXI 15 CY7C1021BN-15VC CY7C1021BN-15VXC CY7C1021BNL-15VXC CY7C1021BN-15ZC CY7C1021BN-15ZXC CY7C1021BNL-15ZC CY7C1021BNL-15ZXC CY7C1021BN-15VI CY7C1021BN-15VXI CY7C1021BN-15ZI CY7C1021BNL-15ZI CY7C1021BN-15ZXI CY7C1021BNL-15ZXI CY7C1021BNL-15ZSXA CY7C1021BN-15VXE CY7C1021BN-15ZSXE 51-85087 51-85082 51-85087 51-85087 51-85082 51-85087 51-85082 51-85082 51-85087 Package Diagram 51-85087 51-85082 Package Type 44-pin TSOP Type II 44-pin (400-Mil) Molded SOJ 44-pin (400-Mil) Molded SOJ (Pb-Free) 44-pin TSOP Type II 44-pin TSOP Type II (Pb-Free) 44-pin (400-Mil) Molded SOJ 44-pin (400-Mil) Molded SOJ (Pb-Free) 44-pin (400-Mil) Molded SOJ 44-pin (400-Mil) Molded SOJ (Pb-Free) 44-pin (400-Mil) Molded SOJ (Pb-Free) 44-pin TSOP Type II 44-pin TSOP Type II (Pb-Free) 44-pin TSOP Type II 44-pin TSOP Type II (Pb-Free) 44-pin (400-Mil) Molded SOJ 44-pin (400-Mil) Molded SOJ (Pb-Free) 44-pin TSOP Type II 44-pin TSOP Type II 44-pin TSOP Type II (Pb-Free) 44-pin TSOP Type II (Pb-Free) 44-pin TSOP Type II (Pb-Free) 44-pin (400-Mil) Molded SOJ (Pb-Free) 44-pin TSOP Type II (Pb-Free) Automotive-A Automotive-E Industrial Commercial Industrial Operating Range Commercial Commercial Package Diagrams 44-pin (400-Mil) Molded SOJ (51-85082) 44 23 DIMENSIONS IN INCHES MIN. MAX. 0.395 0.405 0.435 0.445 1 22 SEATING PLANE 1.120 1.130 0.095 0.115 0.128 0.148 0.023 0.033 0.013 0.023 0.004 0.050 TYP. 0.025 MIN. 0.082 MIN. 0.365 0.375 0-10 0.007 0.013 0.045 MAX. 51-85082-*B Document #: 001-06494 Rev. *A Page 8 of 10 [+] Feedback CY7C1021BN CY7C10211BN Package Diagrams (continued) 44-Pin TSOP II (51-85087) 51-85087-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06494 Rev. *A Page 9 of 10 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1021BN CY7C10211BN Document History Page Document Title: CY7C1021BN/CY7C10211BN (64K x 16) Static RAM Document Number: 001-06494 REV. ** *A ECN NO. Issue Date 423877 505726 See ECN See ECN Orig. of Change NXR NXR New Data Sheet Removed IOS parameter from DC Electrical Characteristics table. Added Automotive products Updated ordering Information table Description of Change Document #: 001-06494 Rev. *A Page 10 of 10 [+] Feedback |
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